Friday, February 24

MS49
How Can Computer Architecture Revolutionize Parallel Scientific Computing

1:00 PM - 3:00 PM
Room: Tudor A/B - 2nd Floor

As we enter the era of billion transistor chips, computer architects face significant challenges in effectively harnessing the large amount of computational potential available in modern CMOS technology. Given the challenges of heat density and resultant stall in clock frequency improvements, chip manufacturers are employing increased on-chip parallelism (multi-core, multi-thread) and increased architectural complexity (VLIW, deep cache hierarchies, stream prefetch) to improve performance. In this minisymposium, leaders in the field of computer architecture research will describe how to reign in architectural complexity and improve scientific productivity on future generations of parallel computing systems using innovative computer architectures.

Organizer: John Shalf
Lawrence Berkeley National Laboratory
David Patterson
University of California, Berkeley

1:00-1:25 How to Hurt Scientific Productivity

David Patterson, University of California, Berkeley

1:30-1:55 Critical Factors and Key Directions For Petaflops Scale Supercomputers

Thomas Sterling, NASA JPL, California Institute for Technolgy, Louisiana State University (CCT)

2:00-2:25 Easy-to-use and Scalable Shared Memory Systems with Transactions

Christos Kozyrakis, Stanford University

2:30-2:55 Infini-T: The Infinite Thread Architecture

Krste Asanovic, Massachusetts Institute of Technology