2020 SIAM Conference on Parallel Processing for Scientific Computing

Part of MS72 Novel Computational Algorithms for Future Computing Platforms - Part III of III
The Rogues Gallery as a Testbed for Novel Algorithm Design for Future Architectures

Abstract. The Rogues Gallery is a new testbed deployment at Georgia Tech for understanding next-generation hardware with a focus on unorthodox and uncommon technologies for what is commonly referred to as post-Moore computing. This testbed project was originally initiated in 2017 in response to IEEE Rebooting Computing efforts and initiatives for new hardware designs. The Gallery's focus is to acquire new and unique hardware (the rogues) from vendors, research labs, and start-ups and to make this hardware widely available to students, faculty, and industry collaborators within a managed data center environment. By exposing students and researchers to this set of unique hardware, we hope to foster cross-cutting discussions about hardware and software design that will drive future performance improvements in computing long after the Moore's Law era of cheap transistors ends.

We present highlights of the first two years of post-Moore era research with the Rogues Gallery. Specifically, we focus on how the Rogues Gallery has supported new algorithm and application development efforts in the areas of near-memory, neuromorphic, and quantum computing with some brief lessons learned on how we can better support future research in these unique research areas.

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